Contact?Barrier Free, High Mobility, Dual?Gated Junctionless Transistor Using Tellurium Nanowire

The gate-all-around nanowire transistor, due to its extremely tight electrostatic control and vertical integration capability, is a highly promising candidate for sub-5 nm technology nodes. In particular, the junctionless transistors are scalable with reduced variability avoidance of steep source/drain junction formation by ion implantation. Here dual-gated p-type field effect transistor demonstrated using tellurium as channel. dangling-bond-free surface unique helical crystal structure nanowire, coupled an dangling-bond-free, high quality hBN gate dielectric, allows phonon-limited hole mobility 570 cm2 V?1 s?1 at 270 K, which well above state-of-the-art strained Si mobility. By lowering temperature, increases 1390 becomes primarily limited Coulomb scattering. combination electron affinity ?4 eV small bandgap provides zero Schottky barrier height injection metal-contact interface, remarkable reduction contact resistance in scaled transistor. Exploiting these properties, operation, we achieve drive current 216 ?A ?m?1 while maintaining on-off ratio excess 2 × 104. findings have intriguing prospects alternate channel material based next-generation electronics.